Metallization interconnects are critical to the proper electronic function of semiconductor devices. Several advances in semiconductor processing have been aimed at improving signal transport speed by reducing metal interconnect resistivities and improving electromigration resistance. Copper has increasingly found application for use as metal interconnects in upper levels of a multi-level device due to its low resistivity and higher resistance to electromigration. However, AlCu metal interconnects used in lower levels of the semiconductor device, for example to provide electrical metal interconnects, is still preferred for a variety of reasons. Among the reason for continued use of AlCu metal interconnects in lower metallization levels is the compatibility of aluminum with silicon including forming superior contacts with lower susceptibility to corrosion. Further, AlCu is readily etched by reactive ion etching (RIE) to form metal interconnects, for example, in the formation of bit lines for a DRAM portion of embedded memory in a logic circuit. In addition, the use of pure copper in lower metallization levels creates the potential of diffusion of copper through dielectric insulating layers and poisoning of doped silicon well areas in transistors by creating deep impurity levels and contributing to junction leakage.
As design rule technology progresses below 0.25 microns, also referred to as sub-quarter micron technology, the ability to achieve complete overlap of metal interconnect lines and underlying metal filled vias is increasingly problematical. Typically, complete overlap is not generally achievable, causing the underlying metal filled via to be partially exposed after forming the overlying metal lines, for example AlCu metal lines formed by a metal etch process.
Tungsten is generally preferred for use in filling vias, also referred to as plugs, in lower levels of a multi-layer semiconductor structures for various reasons including the fact that it provides an effective diffusion barrier to metal diffusion from overlying metallization layers to react with the silicon substrate. Tungsten further has high resistance to electromigration and can effectively be used to fill high aspect ratio vias by chemical vapor deposition (CVD) processes.
One problem with etching overlying metal layers, for example AlCu, in a reactive ion etch (RIE) process is the exposure of a portion of the underlying tungsten plugs. During the metal etching process the plasma process can induce charge imbalance on the wafer surface including a positive charge on the exposed tungsten plug portions. During a subsequent wet stripping process to remove residual photoresist following the etching process, a galvanic reaction of hydroxyl ions with the positively charge tungsten may take place causing the formation of tungsten oxide, e.g., WO2, which has the effect of increasing electrical resistance in addition to causing dissolution and erosion (corrosion) of portions of the tungsten plug. For example, see “A New Failure Mechanism by Corrosion of Tungsten in a Tungsten Plug Process” by S. Bothra et al., Technology Department, VLSI Technology Inc. (1998). As a result, electrical open circuits are formed, creating defective circuitry.
Various approaches have been proposed to reduce the corrosion of tungsten plugs including passivating the exposed tungsten portions with a low pH solution, such as nitric acid, or by using an electron beam to discharge the charged metal plug portions prior to the wet stripping process. Such approaches, however, have not always been effective and may incur undesirable additional operating costs.
While various approaches may be carried out at the end of an RIE etching or ashing process to electrically discharge charged portions of the process wafer, according to prior art processes there has not been used an in-line quantitative process to determine the extent of discharge with respect to selected portions of the wafer. As a result, either portions of the wafer will remain charged or the plasma discharging process is carried out to an excessive extent, reducing wafer throughput
Therefore, there is a need in the semiconductor integrated circuit manufacturing art to develop an electrical monitoring structure and in-line electrical property measurement process to determine an electrical charge state of the process wafer to reduce or avoid circuitry defects including corrosion of tungsten plugs to improve device performance and reliability.
It is therefore an object of the invention to provide an electrical monitoring structure and in-line electrical property measurement process to determine an electrical charge state of the process wafer to reduce or avoid circuitry defects including corrosion of tungsten plugs to improve device performance and reliability, while overcoming other shortcomings of the prior art.